One of the conventional methods for improving the reliability of a common memory, as well as the main memory of each individual computer, is to apply redundancy bits to the memories, thereby to detect errors and correct such errors by correcting the stored data. Although this method provides for an improvement in the reliability of the data stored in the memory by correcting an error of, for example, one bit, for this purpose, the system must be shut down for maintenance of the memory, which is undesirable.
Therefore, a dual arrangement of the common memory has become popular, especially in systems which cannot be shut down, as in the case of a multi-computer system designed for control purposes. In those systems having a dual common memory, the system is operated in the usual manner even when one of the memories becomes disabled so long as the other is working. Thus, the dual common memory as a whole is judged to have failed, only when both of the memories are out of order.
Therefore, for obtaining an improved reliability of the dual common memory, it is essential to shorten the time for repairing the failed memory, i.e., the maintenance time, as much as possible. According to the prior techniques, the failed memory is repaired in the off-line state, while separated from the system, thereby demanding a longer maintenance time, so that the reliability of the dual common memory is not sufficiently made use of. In addition, a specific apparatus or means performing this off-line maintenance must be provided. An on-line maintenance capability would solve these problems, but has not been previously provided.
One example of a system including a dual common memory is disclosed in U.S. Pat. No. 3,668,644, issued on June 6, 1972, entitled "Fail Safe Memory System" and assigned to Burroughs Corporation. However, in this system, there is no on-line maintenance capability for a failed memory module.